| 摘要 |
In a communication device, a counter counts a reference clock CLK1 at each edge of a data signal, and a clock generator generates a reception clock corresponding to the count value of the counter. When there is a frequency lag between the reception clock and the frequency of the transmission clock at a communication partner side, the count value when an edge detection signal is at a H-level is deviated from the count value. This deviation reflects decode signals DS1 to DS3, and phase delay or phase advance is detected on the basis of a signal P1 or P2. At this time, the estimated value of the next edge period is increased/reduced by only "1". When the deviation of the count value occurs sequentially, a frequency excessively-small state or excessively-large state is detected on the basis of the signal F1 or F2. At this time, the estimated count value of the next edge period is increased/reduced by only "2".
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