| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a malfunction-preventing CPU interface circuit capable of avoiding that an erroneous signal generated by noise or the like is falsely recognized as a normal signal and is inputted. <P>SOLUTION: This malfunction-preventing CPU interface circuit has: a synchronizing circuit 11 synchronizing a control signal outputted from an external CPU 50 with a clock signal; and an error decision circuit 12 for the control signal deciding whether the control signal synchronized by the synchronizing circuit 11 has a desired pattern or not. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
