发明名称 |
Method to selectively form poly SiGe P type electrode and polysilicon N type electrode through planarization |
摘要 |
A method for forming selective P type and N type gates is described. A first gate oxide layer is grown overlying a semiconductor substrate. A polysilicon layer is deposited overlying the first gate oxide layer. The polysilicon layer is patterned to form first NMOS gates. A second gate oxide layer is grown overlying the substrate. A polysilicon-germanium layer is deposited overlying the second gate oxide layer and the first gates. The polysilicon-germanium layer and first gates are planarized to a uniform thickness. The polysilicon first gates and the polysilicon-germanium layer are patterned to form second NMOS polysilicon gates and PMOS polysilicon-germanium gates.
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申请公布号 |
US6872608(B1) |
申请公布日期 |
2005.03.29 |
申请号 |
US20030697746 |
申请日期 |
2003.10.30 |
申请人 |
CHARTERED SEMICONDUCTOR MANUFACTURING LTD. |
发明人 |
CHAN TZE HO;BHAT MOUSUMI;CHEE JEFFREY |
分类号 |
H01L21/28;H01L21/8238;(IPC1-7):H01L21/338;H01L21/00;H01L21/823;H01L21/84 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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