发明名称 |
Digital logic module processing period modifying system for use during encryption, has controller tracking number of manipulations of processing circuit, sending select signal to circuit and creating output over N clock cycles |
摘要 |
<p>The system has a processing circuit (400) to receive an input to create an output. A controller (406) is coupled to the processing circuit and configured to track number of manipulations of the processing circuit, send a select signal to the processing circuit and cause the processing circuit to create the output over N clock cycles. An output port (410) is coupled to the processing circuit and configured to convey the output. An independent claim is also included for a method of modifying the number of manipulations in a clock cycle of a digital logic module.</p> |
申请公布号 |
FR2861474(A1) |
申请公布日期 |
2005.04.29 |
申请号 |
FR20030012485 |
申请日期 |
2003.10.24 |
申请人 |
ATMEL CORPORATION |
发明人 |
VERGNES ALAIN |
分类号 |
G06F1/32;G06F9/302;G06F9/318;G06F9/38;G06F13/10;G06F21/55;G06J1/00;H04L9/06;H04L9/18;(IPC1-7):G06F13/10 |
主分类号 |
G06F1/32 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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