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发明名称
半导体积体电路装置之制造方法
摘要
为了提供以均匀膜厚再现性良好地形成高品质且膜厚5nm以下的极薄闸氧化膜之技术,本发明供应低浓度含有因触媒作用而由氢和氧产生之水的氧化种给半导体晶圆主面或其附近,以可确保形成氧化膜的再现性及氧化膜厚的均匀性程度的氧化膜成长速度在半导体晶圆主面形成膜厚5nm以下的氧化膜。
申请公布号
TW200525644
申请公布日期
2005.08.01
申请号
TW094103535
申请日期
1998.02.27
申请人
日立制作所股份有限公司
发明人
田边义和;酒井哲;夏秋信义
分类号
H01L21/318
主分类号
H01L21/318
代理机构
代理人
陈长文
主权项
地址
日本
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