发明名称 |
Method of forming a vertical MOS transistor |
摘要 |
A vertical MOS transistor has a very short channel length that is indirectly defined by the thickness of a layer of semiconductor material or the depths of implants. The transistor has a first (source/drain) region formed in a substrate material, a semiconductor region formed on the first region, and a second (source/drain) region formed in the top surface of the semiconductor region. The distance between the first region and the second region defines the channel length of the transistor.
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申请公布号 |
US6949421(B1) |
申请公布日期 |
2005.09.27 |
申请号 |
US20040880296 |
申请日期 |
2004.06.29 |
申请人 |
NATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
PADMANABHAN GOBI R.;YEGNASHANKARAN VISVAMOHAN |
分类号 |
H01L21/00;H01L21/336;H01L21/8242;H01L21/84;H01L29/78;(IPC1-7):H01L21/00 |
主分类号 |
H01L21/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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