| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To improve reliability and to improve a production yield of a semiconductor integrated circuit. <P>SOLUTION: This clock generation circuit 101 includes: a plurality of dividers 83, 84 respectively dividing a first clock signal to output second clock signals having frequencies different from each other; a reset pulse generation circuit 133 forming a reset pulse synchronized with the first clock signal, capable of resetting the plurality of dividers; and a clock control circuit 200 stopping supply of the first clock signal to the dividers during a reset period of the dividers by the reset pulse. At that time, because it is not necessary to delay a reset signal, a skew margin design between the clock signal and the reset of the divider is not required, and a defective product by margin shortage can be reduced to improve the production yield of the semiconductor integrated circuit. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
