发明名称 DESIGN SYSTEM FOR SEMICONDUCTOR DEVICE AND COST EVALUATION METHOD
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a design system for a semiconductor device which permits the evaluation of finally expected cost at the initial stage of the design of a three-dimensional mounting circuit. <P>SOLUTION: The design system is provided with an arrangement connection information storage means 2 for storing arrangement data, die shape data, terminal data and connection data of each die, a wiring rule storage means 7, a cost calculating formula storage means 10 for storing a cost calculating formula by cost calculation parameters including the height of a stacked die, a step count, a plane view area and a necessary substrate area, a three-dimensional information calculation means 3 for calculating the height of the die, a lamination layer stage count and a plane view area, a wiring terminal coordinate calculating means 5, a virtual wiring means 8 which performs virtual wiring among respective wiring terminals designated by the connection data and calculates a substrate area necessary for the virtual wiring, and a cost calculating means 11 which uses the cost calculation parameters to calculate cost by the cost calculating formula. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p>
申请公布号 JP2005339463(A) 申请公布日期 2005.12.08
申请号 JP20040161062 申请日期 2004.05.31
申请人 FUKUOKA PREF GOV SANGYO KAGAKU GIJUTSU SHINKO ZAIDAN;UENO SEIKI KK;JEDAT INNOVATION:KK;NEW JAPAN RADIO CO LTD;SONY CORP 发明人 TOMOKAGE HAJIME;SAI KUMO;KAWASE EIJI;MIKAMI SONOKO;SHIGEOKA FUMIAKI;KATAOKA HIROYUKI;YOSHIDA SEIICHIRO;ISHIBASHI NAOTO;MATSUOKA TSUGUHIRO;OOTSURU EISAKU;ISERI YOICHI
分类号 G06F17/50;H01L25/065;H01L25/07;H01L25/18;(IPC1-7):G06F17/50 主分类号 G06F17/50
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