Semiconductor device for optoelectronic integrated circuits

摘要

A semiconductor device includes a series of layers formed on a substrate, including a first plurality of n-type layers, a second plurality of layers that form a p-type modulation doped quantum well structure (MDQWS), a third plurality of layers disposed between the p-type MDQWS and a fourth plurality of layers that form an n-type MDQWS, and a fifth plurality of p-type layers. The first plurality of layers includes a first etch stop layer of n-type formed on an n-type contact layer. The third plurality of layers includes a second etch stop layer formed above the p-type MDQWS and a third etch stop layer formed above and offset from the second etch stop layer. The fifth plurality of layers includes a fourth etch stop layer of p-type formed above the n-type MDQWS and a fifth etch stop layer of p-type doping formed above and offset from the fourth etch stop layer.

主权项

1. A semiconductor device comprising:
a series of layers formed on a substrate, the series of layers including:
a first plurality of layers comprising:
an n-type ohmic contact layer; anda first etch stop layer that is formed on the n-type ohmic contact layer;a first spacer layer disposed on the first plurality of layers;a second plurality of layers that form a p-type modulation doped quantum well (QW) structure, wherein the p-type modulation doped QW structure is disposed on the first spacer layer;a third plurality of layers disposed between the p-type modulation doped QW structure and a fourth plurality of layers that form an n-type modulation doped QW structure, the third plurality of layers comprising:
a second etch stop layer formed above the p-type modulation doped QW structure;a second spacer layer disposed on the second etch stop layer;a third etch stop layer formed above the second spacer layer; anda third spacer layer disposed above the third etch stop layer;a fourth spacer layer disposed above the fourth plurality of layers;a fifth plurality of layers comprising:
a fourth etch stop layer formed above the fourth spacer layer;a fifth etch stop layer formed above and offset from the fourth etch stop layer; anda p-type ohmic contact layer formed above the fifth etch stop layer; and a multilayer metal stack formed on at least one of first through third mesas, the multilayer metal stack comprising:
a bottom layer of indium;a layer of nickel deposited on the bottom layer of indium;a layer of tungsten nitride deposited on the layer of nickel; anda top layer of a high temperature metal deposited on the layer of tungsten nitride;wherein:
(i) the first mesa is formed on the second spacer layer,(ii) the second mesa is formed on the fourth spacer layer, and(iii) the third mesa is formed on the n-type ohmic contact layer.