NEURAL NETWORK UNIT WITH NEURAL PROCESSING UNITS DYNAMICALLY CONFIGURABLE TO PROCESS MULTIPLE DATA SIZES

摘要

A neural network unit. A register holds an indicator that specifies narrow and wide configurations. A first memory holds rows of 2N/N narrow/wide weight words in the narrow/wide configuration. A second memory holds rows of 2N/N narrow/wide data words in the narrow/wide configuration. An array of neural processing units (NPU) is configured as 2N/N narrow/wide NPUs and to receive the 2N/N narrow/wide weight words of rows from the first memory and to receive the 2N/N narrow/wide data words of rows from the second memory in the narrow/wide configuration. In the narrow configuration, the 2N NPUs perform narrow arithmetic operations on the 2N narrow weight words and the 2N narrow data words received from the first and second memories. In the wide configuration, the N NPUs perform wide arithmetic operations on the N wide weight words and the N wide data words received from the first and second memories.

主权项

1. A neural network unit, comprising:
a register that holds an indicator that specifies narrow and wide configurations; a first memory that holds rows of 2N narrow or N wide weight words when the indicator indicates the narrow or wide configuration, respectively; a second memory that holds rows of 2N narrow or N wide data words when the indicator indicates the narrow or wide configuration, respectively; and an array of neural processing units (NPU), the array configured as 2N narrow or N wide NPUs and configured to receive the 2N narrow or N wide weight words of rows from the first memory and configured to receive the 2N narrow or N wide data words of rows from the second memory when the indicator indicates the narrow or wide configuration, respectively; when the indicator indicates the narrow configuration, the 2N NPUs are configured to perform narrow arithmetic operations on the 2N narrow weight words and the 2N narrow data words received from the first and second memories; and when the indicator indicates the wide configuration, the N NPUs are configured to perform wide arithmetic operations on the N wide weight words and the N wide data words received from the first and second memories.