Semiconductor arrangement

摘要

A semiconductor arrangement includes a first semiconductor device including a first type region having a first conductivity type and a second type region having a second conductivity type. The semiconductor arrangement includes a second semiconductor device adjacent the first semiconductor device. The second semiconductor device includes a third type region having a third conductivity type and a fourth type region having a fourth conductivity type. The semiconductor arrangement includes a first insulator layer including a first insulator portion around at least some of the first semiconductor device and a second insulator portion around at least some of the second semiconductor device. The first insulator portion has a first insulator height, and the second insulator portion has a second insulator height. The first insulator height is different than the second insulator height. A method of forming a semiconductor arrangement is provided.

主权项

1. A method of forming a semiconductor arrangement, the method comprising:
forming a first nanowire and a second nanowire; forming a first insulator layer between the first nanowire and the second nanowire; etching a first portion of the first insulator layer adjacent the first nanowire to define a first insulator portion having a first insulator height, wherein a second portion of the first insulator layer defines a second insulator portion having a second insulator height different than the first insulator height, the first insulator portion and the second insulator portion both located between the first nanowire and the second nanowire; forming a dielectric layer over a top surface of the first insulator portion and the second insulator portion; and forming a gate electrode over the dielectric layer, wherein:
a portion of a top surface of the gate electrode that overlies the first insulator portion is located at a first height relative to an underlying substrate upon which the first nanowire and the second nanowire are formed,a portion of the top surface of the gate electrode that overlies the second insulator portion is located at a second height relative to the underlying substrate, andthe first height is different than the second height.