Insulating layer for planarization and definition of the active region of a nanowire device

摘要

Various embodiments include methods of fabricating a semiconductor device that include forming a plurality of nanowires on a support, wherein each nanowire comprises a first conductivity type semiconductor core and a second conductivity type semiconductor shell over the core, forming an insulating material layer over at least a portion of the plurality of nanowires such that at least a portion of the insulating material layer provides a substantially planar top surface, removing a portion of the insulating material layer to define an active region of nanowires, and forming an electrical contact over the substantially planar top surface of the insulating material layer.

主权项

1. A method of fabricating a semiconductor device, comprising:
forming a plurality of nanowires on a support, wherein each nanowire comprises a first conductivity type semiconductor core and a second conductivity type semiconductor shell over the core; forming an insulating material layer over at least a portion of the plurality of nanowires such that at least a portion of the insulating material layer provides a substantially planar top surface; removing a portion of the insulating material layer to define an active region of nanowires; forming a conductive material layer over at least a portion of the insulating material layer and the plurality of nanowires in the active region; and forming an electrical contact over the substantially planar top surface of the insulating material layer, wherein: the electrical contact is electrically connected to the conductive material layer; and the conductive material layer comprises a p-electrode which contacts the second conductivity type semiconductor shell of the nanowires in the active region.