Semiconductor device, pre-write program, and restoration program

摘要

When a control circuit has received a first erase command, the control circuit controls performing a first pre-write process to allow a first storage device and a second storage device to have threshold voltages, respectively, both increased, and the control circuit thereafter controls performing an erase process to allow the first storage device and the second storage device to have their respective threshold voltages both decreased to be smaller than a prescribed erase verify level. When the control circuit has received a second erase command, the control circuit controls performing a second pre-write process to allow one of the first storage device and the second storage device to have its threshold voltage increased, and control circuit subsequently controls performing the erase process.

主权项

1. A semiconductor device comprising:
a memory array including a plurality of twin cells each formed of electrically rewritable, first and second storage devices holding binary data depending on a difference between a threshold voltage of said first storage device and a threshold voltage of said second storage device; and a control circuit that controls erasing twin cell data held in said twin cells, when said control circuit has received a first erase command, said control circuit controlling performing a first pre-write process to allow said first storage device and said second storage device to have their respective threshold voltages both increased, said control circuit thereafter controlling performing an erase process to allow said first storage device and said second storage device to have their respective threshold voltages both decreased to be smaller than a prescribed erase verify level, whereas when said control circuit has received a second erase command, said control circuit controlling performing a second pre-write process to allow one of said first storage device and said second storage device to have its threshold voltage increased, said control circuit thereafter controlling performing said erase process.