| 主权项 |
1. A single-poly nonvolatile memory (NVM) cell, comprising:
a select transistor on a first well of a semiconductor substrate, wherein the select transistor comprises a select gate, a first gate oxide layer between the select gate and the semiconductor substrate, a first source/drain doping region in the first well, and a second source/drain doping region spaced apart from the first source/drain doping region; a floating gate transistor on the first well serially connected to the select transistor, wherein the floating gate transistor comprises a floating gate, a second gate oxide layer between the floating gate and the semiconductor substrate, the second source/drain doping region commonly shared by the select transistor, and a third source/drain doping region spaced apart from the second source/drain doping region; a first salicide layer on the first source/drain doping region; a protector oxide layer covering and being in direct contact with the floating gate; a contact etch stop layer on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer; a first sidewall spacer provided on either sidewall of the select gate; and a second sidewall spacer provided on either sidewall of the floating gate, wherein the protector oxide layer covers and is in direct contact with a top surface of the floating gate, surfaces of the second sidewall spacers, entire surface of the second source/drain doping region, and only a portion of the third source/drain doping region. |
