| 摘要 |
<p>1281664 Pulse code modulation systems PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd 19 April 1971 [4 April 1970] 25929/71 Heading H4L In an interference suppression system for PCM signals which may have a varying base level in addition to being affected by white noise the incoming signal on line 4 is combined at 16 with a D.C. potential from a source 14 controlled in accordance with variations in the base level of the incoming signal in relation to a reference potential 15, e.g. earth. The output from 16 is supplied to integrators 2, 3 which are shunted by electronic switches S1, S2 respectively which operate at the bit frequency under the control of pulses from generator 1 so that integration at 2 extends over the bit period and that at 3 is staggered by half a bit period. The outputs of the integrators are supplied to a circuit 11 which detects the zero crossings in relation to the reference level, the integrators also forming part of a control loop for phase adjustment of the clock generator 1 and of a second control loop for the voltage source 14 to maintain the reference level and the varying D.C. level of the received signals equal. In the circuit 11, Fig. 3, the outputs of the integrators are compared at 17, 18 respectively with the reference voltage 15 whereby a voltage occurs at the J inputs of bi-stable registers 23, 26 when the output level of integrators 2, 3 is above the reference level and at the K inputs when the outputs are below. Integrator 2 and register 23 are controlled by pulses a, Fig. 4, from the generator 1 and integrator 3 and register 26 are controlled by pulses b. The generator 1 is phase controlled so that pulses a coincide with the transitions of the incoming pulses d shown in idealized form. Pulses c are phase shifted by a small amount relative to pulses a and control a further register 24. Fig. 4 shows the condition when the D.C. level and pulses a coincide with the signal pulse transitions e at the output of integrator 2. An input at J of register 23 produces binary 1 at output Q1, providing the reconstituted signal pulses, and binary 0 at output Q2 and the converse (h) occurs with an input at K. A register 24 controlled by pulses c, takes the outputs of register 23 and via an exclusive OR gate 27 provides pulses l representing signal transitions which are supplied to AND gates 33 to 36 controlled in dependence on phase error and D.C. voltage level error as determined by the output f of integrator 3 controlled by pulses b which coincide with the centre of a bit period. Considering output f, the output value at each of the clock pulses b is equal to the reference level and the positive and negative portions cancel each other. When the direct voltage level and/or the phase is incorrect these positive and negative portions no longer cancel, Figs. 5, 6 (not shown) and correction signals are derived, the comparator 18 detecting both types of error. Either or both types of error are registered at 26 an output being provided at Q1 or Q2 in dependence on the direction of the error, the polarity of the deviation of the D.C. level remaining equal at successive registering instants while the deviation in the case of a phase error changes its polarity at successive registering instants. Output Q1 enables AND gate 36 when the D.C. level is too low and output Q2 enables AND gate 35 when it is too high, gates 35, 36 causing the voltage derived at source 14 to be decreased or increased by one step as required. The source 14 may be a bi-directional counter followed by a digital-to-analogue converter. If the D.C. voltage level is correct but the phase is not yet correct, gates 35, 36 are enabled alternately so that no correction of the voltage level is effected. The direction of the deviation signal from comparator 18 in relation to the direction of a signal transition is determined by the direction of the phase error and this enables AND gates 33, 34 to be controlled to shift the clock pulse generator 1 one step forward or one step. backward as required. For this purpose the values stored in register 23 are transferred to a register 25 at the instant register 26 is operated and the signals at outputs Q1, Q2 of these registers are selected by Exclusive OR circuits 28, 29, so that a signal at the output of circuit 29 enables AND gate 34 so long as the clock pulses lag in phase and a signal at the output of circuit 28 enables AND gate 33 of the clock pulses to lead in phase. If the phase is correct but the D.C. level requires correction, gates 33, 34 are operated alternately.</p> |
