TIMING MONITOR CIRCUIT FOR CENTRAL DATA PROCESSOR OF DIGITAL COMMUNICATION SYSTEM

摘要

Circuitry is disclosed for monitoring the timing pulse levels in a digital communications system having duplicate central processors, only one of which may be active at any given time. The circuitry senses the repetition rate of a given timing level and generates an error signal as the period pulses occur at intervals more than a predetermined time apart. Further, the circuitry checks all individual place and accept levels from the timing generator circuit to insure that they occur in the proper sequence and that no place or accept levels are missing.