| 摘要 |
<p>An enabling signal for a trigger control logic gate is changed from a non enabling level to an enabling level by a flip-flop actuated by an output from a second gate when a holdoff signal from a triggered circuit applied to an input of the second gate changes from a holdoff level to a non holdoff level during the time interval when an input trigger signal from a trigger circuit, also applied to an input of the second gate, is at a non triggering level. The input trigger signal is also applied to another input of the trigger control gate and timed so that the non triggering level of such signal prevents a triggering operation by such gate during the time interval when a change of the enabling signal to its enabling level can be delivered to such gate. The timing of the application of input triggering signal to the trigger control gate is such that a change of such signal to a triggering level occurs only after the time interval referred to. The triggering operation of the trigger control gate causes the flip-flop to be reset to change the enabling signal back to its original level and also resets another flip-flop to produce the output signal, the second flip-flop having been previously set by the holdoff signal.</p> |
