| 摘要 |
1504097 Printed circuits HONEYWELL INFORMATION SYSTEMS Inc 23 March 1976 [26 March 1975] 11589/76 Heading H1R A multi-layer electronic circuit package 14 (Fig. 1) comprises plural integrated circuit semiconductor devices 10 mounted on its upper surface 12. The input and output of each circuit are each connected to pads 16 of the surface over leads 18; the pads being spaces round each semi-conductor device by incremental S or integral multiples thereof (Fig. 2) in a grid pattern 19. Underlying planes 20, 22 carry sets of equally spaced parallel lines respectively orthogonal one to the other, the spacing W being S/2 and defining a W spaced grid work positioned so that each intersection underlies a corresponding pad, as shown, e.g., by projections 24, 30, 32, 34, 36 which also intersect every other line on one of the conductive planes. Interpolated lines, e.g. 40, 46, define unconnected circuit paths underlying the semi-conductor devices which enable other circuits to be defined, and are interconnected by, e.g., lines 48. In manufacture an alumina substrate 60 (Fig. 3) is formed with W-spaced conductive lines 62 by silk screening a gold and silicate glass frit in an organic binder over a photosensitive mask and firing. A dielectric layer 64 is superimposed by silk screening a dielectric paste over a photosensitive mask to leave via holes 66 spaced by W and overlying the lines 62. The layer is dried at high temperature and a further layer is deposited over the same mask; after which the via holes are filled with gold to interconnect with lines 62 at 70. A further series of spaced conductive lines 72 is applied in plane 20 at right-angles to lines 62 and contact certain of the interlayer conductors 70 for electrical connection. A further dielectric layer 74 is then deposited over a mask in similar manner to the first, and the spaced via holes 76 are filled with gold as before to form interconnections 78, over which pads 16 are correspondingly deposited in plane 12 extending to the conductive lines 62, 72 of planes 20, 22. Base mounts 82 are formed on plane 12; the formation being by silk screening with gold glass frit paste, drying depositing solder thereon, and heating to establish connection with respective semi-conductor pads 10 and leads 18 placed in contact therewith. Other circuitry may be similarly placed on plane 12 and interconnected over conduits 66, 75 to lines 62, 70 while further dielectric may be superimposed on plane 12 with appropriate via hole contacts for further circuitry carried thereon. |
