Fast exit from DRAM self-refresh

摘要

Embodiments of the invention describe a dynamic random access memory (DRAM) device that may abort a self-refresh mode to improve the exit time from a DRAM low power state of self-refresh. During execution of a self-refresh mode, the DRAM device may receive a signal (e.g., a device enable signal) from a memory controller operatively coupled to the DRAM device. The DRAM device may abort the self-refresh mode in response to receiving the signal from the memory controller.

主权项

1. A system comprising:
a dynamic random access memory (DRAM) device, the DRAM device including
a memory array, andcontrol logic coupled with the memory array, the control logic capable to abort a self-refresh responsive, at least in part, to a self-refresh exit command, wherein the DRAM device capable to be selectively enabled to abort self-refresh; and a memory controller coupled with the DRAM device, the memory controller capable to issue a valid command subsequent to the self-refresh exit command, wherein a time from the self-refresh exit command to issuance of the valid command is tXS if the DRAM is not enabled to abort self-refresh, and is less than tXS if the DRAM is enabled to abort self-refresh.