| 发明名称 |
HIGHHSPEED CIRCULAR*SERIAL DATA TRANSMISSION SYSTEM |
| 摘要 |
<p>PURPOSE:The clock signal is inverted from master equipment to slave equipment to be sent back to master equipment as a clock signal. As a result, the duty ratio of the clock signal is compensated and the clock width margin is increased, ensuring high-speed operation.</p> |
| 申请公布号 |
JPS5244107(A) |
申请公布日期 |
1977.04.06 |
| 申请号 |
JP19750118845 |
申请日期 |
1975.10.03 |
| 申请人 |
HITACHI LTD |
发明人 |
KOBAYASHI YOSHIKI;BANDOU TADAAKI;USAMI ISAO |
| 分类号 |
H04L29/08;H04L7/00;H04L7/04 |
主分类号 |
H04L29/08 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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