发明名称 |
Trap rich layer formation techniques for semiconductor devices |
摘要 |
A trap rich layer for an integrated circuit chip is formed by chemical etching and/or laser texturing of a surface of a semiconductor layer. In some embodiments, a trap rich layer is formed by a technique selected from the group of techniques consisting of laser texturing, chemical etch, irradiation, nanocavity formation, porous Si-etch, semi-insulating polysilicon, thermal stress relief and mechanical texturing. Additionally, combinations of two or more of these techniques may be used to form a trap rich layer. |
申请公布号 |
US9515139(B2) |
申请公布日期 |
2016.12.06 |
申请号 |
US201514746398 |
申请日期 |
2015.06.22 |
申请人 |
QUALCOMM Incorporated |
发明人 |
Arriagada Anton;Stuber Michael A.;Molin Stuart B. |
分类号 |
H01L21/30;H01L29/06;H01L21/02;H01L21/20;H01L21/84;H01L29/78;H01L27/12;H01L21/268;H01L21/304;H01L21/306;H01L21/762 |
主分类号 |
H01L21/30 |
代理机构 |
Haynes and Boone, LLP |
代理人 |
Haynes and Boone, LLP |
主权项 |
1. A method comprising:
forming a damaged layer for an integrated circuit by scanning a laser beam in a pattern across a first wafer; forming a circuit layer for the integrated circuit in a second wafer; and bonding the first wafer to a top side of the second wafer; wherein the damaged layer has a trap density of greater than 1011 cm−2 eV−1; and wherein the damaged layer is located between the circuit layer and a substrate of the integrated circuit. |
地址 |
San Diego CA US |