MEMORY CONTROL SYSTEM

摘要

MEMORY CONTROL SYSTEM A group of asynchronous memories are interconnected to a CPU and the I/O terminal (data channel) in a minicomputer. The memories send "handshaking" signals to the data channel and the CPU by means of a common signalling system having common signalling lines, one line to the data channel and one line to the CPU, to define the status of any of the memories, depending on the memory which is addressed, by acknowledging requests by that memory, with respect to a data bus and indicating receipt of data by the memory. The CPU and data channel in turn, signal each of the memories by means of a common set of signal lines to determine each memory's status and to cause the output of the aforementioned memory signals.