发明名称 SERIALLPARALLEL CONVERSION SYSTEM
摘要 PURPOSE:To realize a high-speed conversion from the serial data into the parallel data by securing the byte-based processing even through the serial data is directly written into the frame memory. CONSTITUTION:Bit d11 of the serial data is written with the contents of the frame memory into each of addresses 1i, 2j, 3k, 4e, 5m, 6n, 7o and 8p each, that is, the writing is carried out for one bit in a speed of 8 times as high as conventional and with the sequential shift of the writing addresses in the oblique direction. As a result, the writing of the serial data is idential to the case in which the data is written with every 8 bytes like a, i and q, and the contents which are shifted by one bit emerge every 8 bytes like b, j and r. According to such frame memory contents, the position where the head of the word becomes the head address of the byte is detected. Then the contents of the frame memory can be read out every 8 bytes. As a result, a high-speed conversion becomes possible into the parallel data although the capacity of the frame memory is increased.
申请公布号 JPS5534544(A) 申请公布日期 1980.03.11
申请号 JP19780106768 申请日期 1978.08.31
申请人 FUJITSU LTD 发明人 KANAMARU HISAFUMI;HATA FUSAO;YAMADA HISASHI
分类号 H03M9/00;G06F5/00;G06F13/00;H04L13/10 主分类号 H03M9/00
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