发明名称 Processor controlled telecommunication switching system
摘要 Each memory individually associated with a respective one of two processors of a centrally controlled switching system incorporates status buffers. Information relating to each call is stored in a pair of status buffers in each memory, the status buffers of each pair being interlinked by linkage information. In case of a partial or a total breakdown of the system without the memory of at least one processor being affected, a special recovery program is executed by the latter processor to clear not only all the calls which are not in conversation, or not in a supervision phase, but also all the calls in a conversation phase for which pairs of associated status buffers contain erroneous linkage information.
申请公布号 US4207437(A) 申请公布日期 1980.06.10
申请号 US19740508416 申请日期 1974.09.23
申请人 INTERNATIONAL STANDARD ELECTRIC CORP 发明人 JANSSENS, JULIAN L G
分类号 H04Q3/545;(IPC1-7):H04Q3/54 主分类号 H04Q3/545
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