Inversely proportional voltage-delay buffers for buffering data according to data voltage levels

摘要

Inversely proportional voltage-delay buffers for buffering data according to data voltage levels are disclosed. In one aspect, an inversely proportional voltage-delay buffer is configured to buffer a data signal for an amount of time that is inversely proportional to a voltage level of the data signal. The inversely proportional voltage-delay buffer includes an inversion circuit and pass circuit. The inversion circuit is configured to generate a control signal that is the logic inverse of the data signal. Notably, the control signal transitions at a rate proportional to the voltage level of the data signal. The pass circuit is configured to generate a weak logic state of the data signal when the data signal and the control signal have the same logic state. The pass circuit is configured to generate a strong logic state of the data signal when the data input and the control signal have opposite logic states.

主权项

1. An inversely proportional voltage-delay buffer, comprising:
an inversion circuit configured to generate a control signal having an inverted logic state of a data input signal, wherein a transition rate of the control signal is proportional to a voltage level of the data input signal; a pass circuit, comprising:
a first pass device, configured to:
generate a data output signal having a weak logic state of the data input signal in response to the data input signal and the control signal having a first logic state; andgenerate the data output signal having a strong logic state of the data input signal in response to the control signal having the first logic state and the data input signal having a second logic state, wherein the second logic state is opposite of the first logic state; anda second pass device, configured to:
generate the data output signal having a weak logic state of the data input signal in response to the data input signal and the control signal having the second logic state; andgenerate the data output signal having a strong logic state of the data input signal in response to the control signal having the second logic state and the data input signal having the first logic state.