Row decoder for non-volatile memory devices and related methods

摘要

An integrated circuit includes an array of phase-change memory (PCM) cells, a plurality of wordlines coupled to the array of PCM cells, and a row decoder circuit coupled to the plurality of wordlines. The row decoder circuit includes a first low voltage logic gate and a first high voltage level shifter coupled to the first low voltage logic gate. The row decoder circuit also includes a second low voltage logic gate, a second high voltage level shifter coupled to the second low voltage logic gate, and a first low voltage logic circuit coupled to the second low voltage logic gate. In addition, the row decoder circuit includes a second low voltage logic circuit coupled to the second low voltage logic gate, and a low voltage wordline driver having an input coupled to the outputs of the first and second low voltage logic gates, and an output coupled to a selected wordline.

主权项

1. An integrated circuit comprising:
an array of phase-change memory (PCM) cells; a plurality of wordlines coupled to the array of PCM cells; and a row decoder circuit coupled to the plurality of wordlines, the row decoder circuit comprising
a first low voltage logic gate,a first high voltage level shifter having an output coupled to an input of the first low voltage logic gate, the high voltage being greater than the low voltage,a second low voltage logic gate,a second high voltage level shifter having an output coupled to an input of the second low voltage logic gate,a first low voltage logic circuit having an output coupled to the input of the second low voltage logic gate,a second low voltage logic circuit having an output coupled to the input of the second low voltage logic gate, anda low voltage wordline driver having an input coupled to the outputs of the first and second low voltage logic gates, and an output coupled to a selected wordline of the plurality of wordlines.