| 摘要 |
PURPOSE:To realize a high-operation reliability JK flip flop circuit where yield is improved and cost is reduced, by giving a prescribed delay to clocks for data entry. CONSTITUTION:Dummy gate 21 is provided as a means to give a delay to clock input CLKd for data entry. Due to existence of dummy gate 21, the delay dependent upon dummy gate passage is given to the clock system for data entry equivalently to the delay dependent upon gate passage generated inevitably in the clock system for trigger. Dummy gate 21 can be realized if a needless unused gate is used as it is in a LSI. Then, since the passage delay quantity of gate unit is constant approximately in respect to any gate, unstable elements are eliminated. |
