发明名称 |
Dynamically controlling cache size to maximize energy efficiency |
摘要 |
In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed. |
申请公布号 |
US9471490(B2) |
申请公布日期 |
2016.10.18 |
申请号 |
US201514840639 |
申请日期 |
2015.08.31 |
申请人 |
Intel Corporation |
发明人 |
Ananthakrishnan Avinash N.;Rotem Efraim;Weissmann Eliezer;Rajwan Doron;Shulman Nadav;Naveh Alon;Abu-Salah Hisham |
分类号 |
G06F12/00;G06F12/08;G06F1/28 |
主分类号 |
G06F12/00 |
代理机构 |
Trop, Pruner & Hu, P.C. |
代理人 |
Trop, Pruner & Hu, P.C. |
主权项 |
1. A processor comprising:
a first domain including a plurality of cores to independently execute instructions; a second domain including at least one graphics engine; a cache memory coupled to the plurality of cores and including a plurality of partitions; and a power controller coupled to the first domain and the cache memory, wherein the power controller includes a first logic to dynamically vary a size of the cache memory based at least in part on a memory boundedness of a workload to be executed on at least one of the plurality of cores, and to cause at least one of the plurality of partitions to be powered with a retention voltage to maintain a state of the at least one core of the plurality of cores when the processor is in a package low power state in which the first domain and the second domain are in a low power state. |
地址 |
Santa Clara CA US |