| 主权项 |
1. An apparatus comprising:
a scheduler configured to issue instructions to one or more functional units, wherein the scheduler is configured to utilize counters to manage protection of source operands; and a functional unit coupled to a queue having a number of slots for storing instructions, wherein instructions issued to the functional unit are stored in the queue until the functional unit is available to process the instructions, wherein the counters comprise a read counter and a write counter associated with each register of a register file, and wherein the read counter for a particular register is incremented when an instruction specifying the particular register as a source operand is issued to the functional unit and decremented when the source operand is read from the register file, and wherein the write counter for the particular register is incremented when an instruction specifying the particular register as a destination operand is issued to the functional unit and decremented when an output for the instruction is written to the register file, and wherein the scheduler, the one or more functional units, and the queue are included in a processor. |
