| 摘要 |
A register circuit for processing information in accordance with a given instruction set or set of transformation comprises N registers each having an input and an output and provided in a sequence R1, R2, R3, . . . RN, each register having n digits where N and n are integers. The output of the first register R1 is connected to a first bus while its input is connected to a second bus. All of the other registers R2, R3, . . . RN have their inputs connected to the first bus and their outputs to the second bus by respective strobe circuits. The strobe circuits of each of the buses R3 . . . RN are connected to respective control inputs a3 . . . aN. Additional control inputs a1 and a2 are connected to an OR-gate whose output is applied to the input strobe circuit of register R2 while the input a2 is also applied directly to the output strobe circuit of register R 2. This allows transfer of the contents of the first register to the second upon the application of a signal to the input a1 and parallel transfer between all the registers by the appropriate control inputs. |
