| 摘要 |
PURPOSE:To provide an SITL having low power and high operating speed by forming electrically and independently the P-type collector of a lateral PNP transistor and the P-type gate of a switching SIT through an insulating layer. CONSTITUTION:N<+>-type buried layers 11a, 11b are formed on a P-type substrate 30, N<->-type epitaxial layers 21a, 21b are laminated thereon, and isolated with an SiO2 layer 29. Then, P-type layers 25a, 25b, and 24 are selectively formed in the N-type epitaxial layer, and N<+>-type drains 23a, 23b are formed in predetermined region becoming channel at the openings of the layer 24. Simultaneously, N<+>-type base 23c and source 23d are formed. In this case, the layers 24, 23a, 23b are retained at predetermined interval. Then, aluminum electrode is selectively provided to complete an SITL. With this configuration the lateral PNP transistor 103 being heretofore current source and the switching SIT 104 being load are independently formed through an insulator 29. When the base of the lateral PNP element is set slightly higher in potential than the source of the SIT, the saturation of the element 103 can be eliminated to suppress the storage of the minority carrier so as to execute high speed operation with low consumption power in an SITL. |
