| 摘要 |
PURPOSE:To obtain a stable modulated signal with a small number of parts by using a memory that assigns a counter number according to the 1 and 0 sequence of an input data signal and a counter that inverts an output at intervals of the count number. CONSTITUTION:Memory 21 outputs a signal that assigns count number N1 to input data [1] and N2 to input data [0]. Counter 22, on the other hand, inverts outputs [1] and [0] according to the counter assignment signal of this memory 21 and oscillator 23 outputs a stable clock signal of frequency fp. Therefore, when input data is [1], the outputs are inverted at intervals of count number N1 to generate a signal of T1=2N1/fp in period and when [0], a signal of T2=2N2/fp is outputted, generating an FSK signal. |
