| 摘要 |
PURPOSE:To contrive the improvement in the performance of a semiconductor device and the increase in the density thereof by forming the gate electrode of a complementary insulated gate FET of an N type polysilicon and also forming most electrode wirings except a part of the polysilicon. CONSTITUTION:A P<-> type layer 2 is formed on an N<-> type Si substrate 1, N<+> type layers 3, 4 are formed in the layer 2, and P<+> type layers 9, 10 are formed in the substrate 1. A gate oxide film 5 and a field oxide film 16 are covered with an N<+> type polysilicon 25. Subsequently, a BSG26 is formed on the layers 9, 10, a B is diffused therein, and the polysilicon 25 directly thereunder is transformed into a P<+> type layer 27. Then, aluminum 28 is evaporated thereon, is selectively etched, and there are formed on the respective gate films 5 gate electrodes 29, 30, source electrodes 31, 32 with N type polysilicon and wire 33 for connecting the layer 4 to the layer 10. When P type and N type polysilicons 25, 27 having different etching speeds are plasma etched together with the aluminum 28, they can be etched in the same width. Eventually, an SiO2 film 34 is covered thereon, and it is completed. According to this configuration the C-MOS can be provided with stable gate, its wiring resistance can be lowered, and there can be obtained a complmentary semiconductor device which has high performance and high integrity. |
