Variable resistance memory device

摘要

A variable resistance memory device includes upper interconnections on a substrate, first and second word lines provided between the substrate and the upper interconnections and vertically spaced apart from each other, a first bit line disposed between the first and second word lines and intersecting the first and second word lines, memory cells provided in an intersecting region of the first word line and the first bit line and an intersecting region of the second word line and the first bit line, a first word line contact directly connecting the first word line to a corresponding one of the upper interconnections, and a second word line contact directly connecting the second word line to a corresponding one of the upper interconnections.

主权项

1. A variable resistance memory device comprising:
upper interconnections on a substrate; a first word line and a second word line between the substrate and the upper interconnections, the first and second word lines spaced apart from each other in a direction that is perpendicular to a top surface of the substrate; a first bit line disposed between the first word line and the second word line, the first bit line intersecting the first and second word lines; memory cells provided in an intersecting region of the first word line and the first bit line and an intersecting region of the second word line and the first bit line; a first word line contact comprising a first unitary member directly connecting the first word line to a first one of the upper interconnections, wherein the first unitary member is in direct contact with the first word line and the first one of the upper interconnections, and a lowermost surface of the first unitary member is disposed at a level higher than that of a bottom surface of the first word line from the substrate; and a second word line contact comprising a second unitary member directly connecting the second word line to a second one of the upper interconnections, wherein the second unitary member is in direct contact with the second word line and the second one of the upper interconnections, and a lowermost surface of the second unitary member is disposed at a level higher than that of a bottom surface of the second word line from the substrate, wherein the first word line is connected to a first peripheral circuit through the first word line contact and the first one of the upper interconnections that is connected to the first word line contact, and wherein the second word line is connected to the first peripheral circuit through the second word line contact and the second one of the upper interconnections that is connected to the second word line contact.