发明名称 SISTEMA DE RETENCION DE DATOS EN CIRCUITOS DIGITALES
摘要 <p>The power supply circuit for a digital circuit, e.g. a microprocessor, branches 2 to form two power supply lines V1, V2. One line V1 supplies volatile low-power consuming components of the circuit and is connected to a high valued earthed capacitor C1 which sustains the supply during a temporary power failure. The other line V2 supplies the remainder of the circuit including high power consuming components and is arranged to cease supplying power rapidly in response to power failure. A third branch may continue to supply power to a memory to which data is transferred on detection of a power failure. <IMAGE></p>
申请公布号 ES497910(D0) 申请公布日期 1981.09.16
申请号 ES20100004979 申请日期 1980.12.18
申请人 MERLONI ELECTRODOMESTICI S.P.A. 发明人
分类号 G05F1/577;G06F11/20;(IPC1-7):02J9/00;11C11/00 主分类号 G05F1/577
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