Methods related to frequency synthesis control

摘要

Disclosed are systems and method for controlling frequency synthesizers. A control system can be implemented in a phase-locked loop (PLL), such as a Frac-N PLL of a frequency synthesizer, to reduce or eliminate reference spurs. In some embodiments, such a control system can include a phase detector configured to receive a reference signal and a feedback signal. The phase detector can be configured to generate a first signal representative of a phase difference between the reference signal and the feedback signal. The control system can further include a charge pump configured to generate a compensation signal based on the first signal. The control system can further includes an oscillator configured to generate an output signal based on the compensation signal. The compensation signal can be configured to reduce or substantially eliminate one or more reference spurs associated with the frequency synthesizer.

主权项

1. A method for controlling a frequency synthesizer of a wireless device, the method comprising:
receiving, by a phase detector, a reference signal and a feedback signal; generating a current signal based at least in part on a phase difference between the reference signal and the feedback signal; performing a logic operation between a signal representative of the phase difference and a switch signal to generate a charge signal; charging, by a charge pump, a capacitance element upon receipt of the charge signal to provide a voltage representative of the phase difference; generating a voltage signal based on the current signal; and generating an output signal based on the voltage signal to reduce or substantially eliminate one or more spurs associated with the frequency synthesizer.