发明名称 ROBUST AND RESILIENT TIMING ARCHITECTURE FOR CRITICAL INFRASTRUCTURE
摘要 A device for transmitting synchronized timing including a receiver, a transmitter, one or more processors, memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the programs including instructions for receiving through the receiver a timing signal comprising first time information that is synchronized to a time standard, determining second time information based at least partially on the first time information, composing a message formatted in accordance with a global navigation satellite system (GNSS) standard, wherein the message comprises the second time information, and transmitting the message through the transmitter on a radio signal having a frequency in the frequency modulation (FM) radio frequency band.
申请公布号 US2016306048(A1) 申请公布日期 2016.10.20
申请号 US201514690225 申请日期 2015.04.17
申请人 The MITRE Corporation 发明人 DUNN Jeffrey;McKENNA Sean;MARTIN Cynthia E.;COHEN Michael L.
分类号 G01S19/10;G01S19/20 主分类号 G01S19/10
代理机构 代理人
主权项 1. A device for transmitting synchronized timing comprising: a receiver; a transmitter; one or more processors; memory; and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the programs including instructions for: receiving through the receiver a timing signal comprising first time information that is synchronized to a time standard; determining second time information based at least partially on the first time information; composing a message formatted in accordance with a global navigation satellite system (GNSS) standard, wherein the message comprises the second time information; and transmitting the message through the transmitter on a radio signal having a frequency in a frequency modulation (FM) radio frequency band.
地址 McLean VA US