发明名称 CHAINING CHECK SYSTEM
摘要 PURPOSE:To execute a chaining check by use of a comparing circuit consisting of a simple structure, by checking whether a readout address register and a write address register are in coincidence or not, at a coincidence time point. CONSTITUTION:A byte counter value (n) of a channel control word CCW1 is set to a terminal register END, and a read input/output operation is executed. When the register END coincides with a register MSA, a request for instructing a data transfer and chain data is sent out to a CPU. As a result, the next channel control word CCW2 is fetched, and when data of quantity designated by the control word CCW2 is stored in a main memory, a comparing circuit COMP1 outputs a coincidence signal. At this time point, if a comparing circuit COMP2 shows dissidence, a chaining check signal of ''1'' is generated.
申请公布号 JPS57105018(A) 申请公布日期 1982.06.30
申请号 JP19800182198 申请日期 1980.12.22
申请人 FUJITSU KK 发明人 HIROWATARI SHIYOUICHI;SUZUKI OSAMU;NISHIMURA KOUSUKE;SAITOU HIDEFUSA
分类号 G06F11/30;G06F13/00;G06F13/10 主分类号 G06F11/30
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