| 摘要 |
PURPOSE:To eliminate a high-speed memory by obtaining a test pattern which varies at an (n)-fold speed by making the operation speed of a pattern generation part higher than those of a command part and an operand part. CONSTITUTION:A test-pattern generator is equipped with a 1/N frequency divider 312 clock pulses 411, a program counter 115 preset by its frequency-division output pulses 412, a command part 112 and an operand part 113 which are accessed by the output of the counter and output next address information, a means 117 which calculates a next address by the address information of the parts 112 and 113 and presets the counter 115 by supplying the arithmetic result, an N-scale counter 311 which counts the pulses 411, and a pattern generation part 114 whose low-order digit bits are accessed by the counter 311 while the high-order digit bits are accessed by the counter 115. Then, a data pattern and an address pattern are read out of the generation part 114 at a frequency (n) times as high as the readout frequency of the command part 112 and operand part 113. |
