| 摘要 |
PURPOSE:To transfer data, which has multiple data format like doubled-precision floating-point data and fixed-point data, through a less number of buses by using the same aligning circuit. CONSTITUTION:At the high-order digit parts and low-order digit parts of input registers IR-0-IR-3, split input section data MI-0-MI-7 are provided, and their outputs are transferred to output section data M0-1, M0-3, M0-5, and M0-7. An aligning circuit 3 requires only 32 buses for 4-byte data transfer between the section data. For 8-byte data transfer, output section data M0-0, M0-2, M0-4, and M0--6 are provided, and between those data and said input section data MI-0, MI-2, MI-4, and MI-6, 4 4-byte buses each, i.e. 16 buses in all are required. Consequently, the aligning circuit 3 manages with 52 buses for 4-byte transfer. |
