Testing I/O timing defects for high pin count, non-contact interfaces

摘要

Indirect testing of multiple I/O interface signal lines concurrently. A system distributes a test data sequence to a group of signal lines. Each signal line receives the test data sequence and checks for errors in receiving the test data sequence at an associated I/O buffer. The system includes an error detection mechanism for each signal line. The system also includes an error detection mechanism for the group of multiple signal lines. If the I/O buffer receives any bit of the test data sequence incorrectly, the signal line error detection indicates an error. The group error detection accumulates pass/fail information for all signal lines in the group. Rather than sending a pass/fail indication on every cycle of the test, the group error detection can count pass/fail information for all signal lines of the group for all bits of the test data sequence and indicate error results after the entire test data is received.

主权项

1. A method for testing an I/O (input/output) interface, comprising:
receiving a test data sequence at a hardware interface of a device under test from a test source separate from the device under test; distributing each bit of the test data sequence concurrently to each signal line of a group of multiple signal lines, each signal line interfacing a hardware I/O buffer of the device under test, wherein the multiple signal lines of the group share a common timing signal; testing for errors at each hardware I/O buffer, including detecting an error for any signal line when the signal line does not receive a bit of the test data sequence correctly for a given timing setting; accumulating pass/fail data for all signal lines of the group at the device under test based on the detected errors; and sending a pass/fail indication value to the test source from the device under test only after accumulating pass/fail information for all bits of the test data sequence for all the signal lines of the group.