发明名称 Array substrate, liquid crystal display panel and display device
摘要 An array substrate, a LCD panel and a display device are disclosed. The array substrate includes: a substrate, a plurality of pixels disposed on the substrate and defined by a plurality of gate lines and a plurality of data lines. A common electrode and a pixel electrode are disposed in each pixel region. Two pixels at adjacent rows in a same column form a pixel set. A first gate line and a second gate line are disposed between the two pixels of the pixel set. The data line is disposed on the same side of the two pixels. A first switch transistor and a third switch transistor are disposed in one pixel region of the pixel set and at least a second switch transistor is disposed in the other pixel region.
申请公布号 US9500922(B2) 申请公布日期 2016.11.22
申请号 US201314367841 申请日期 2013.12.05
申请人 BOE Technology Group Co., Ltd.;Hefei BOE Optoelectronics Technology Co., Ltd. 发明人 Jiang Qinghua;Qin Feng;Li Xiaohe;Shao Xianjie;Liu Yong
分类号 G02F1/136;G02F1/1362 主分类号 G02F1/136
代理机构 Banner & Witcoff, Ltd. 代理人 Banner & Witcoff, Ltd.
主权项 1. An array substrate, comprising: a substrate; a plurality of pixel regions disposed on the substrate and defined by a plurality of gate lines and a plurality of data lines; and a common electrode and a pixel electrode disposed in each of the plurality of pixel regions, two pixel regions at adjacent rows in a same column form a pixel set, a first gate line and a second gate line are disposed between the two pixel regions of the pixel set, and the data line is disposed on a same side of the two pixel regions, wherein a first switch transistor and a third switch transistor are disposed in one pixel region of the pixel set and at least a second switch transistor is disposed in another pixel region, wherein gate electrodes of the first and second switch transistors are respectively connected to the first gate line and the second gate line, source electrodes of the first and second switch transistors are both connected to a same data line, and drain electrodes of the first and second switch transistors are respectively connected to a pixel electrode in their respective pixel region, and wherein a gate electrode of the third switch transistor is connected to the first gate line, a source electrode of the third switch transistor is connected to a common electrode in the pixel region having the third switch transistor, and a drain electrode of the third switch transistor is connected to a pixel electrode in the pixel region having the second switch transistor.
地址 Beijing CN