| 摘要 |
PURPOSE:To perform efficient operations to improve the processing speed, by controlling the clock of an operation pipeline part only when register numbers of a vector register, from which data is read out, and a vector register to which data is loaded coincide with each other. CONSTITUTION:Only when a register number 22 of a vector register, from which vector data is read out, storing vector data to be supplied to an operation pipeline part and a register number 21 of a vector register to which vector data is written by a load pipeline part coincide with each other as the result of comparison, the clock of this operation pipeline part is controlled, and clocks of other operation pipeline parts are not stopped. |
