ENCODING SYSTEM FOR TRANSMISSION LINE

摘要

PURPOSE:To suppress the continuity of the same code, by inserting two bits, which consist of the combination of a one-bit mark and a one-bit space and have the relation of NOT to each other, at every interval of a certain number of bits to constitute a frame. CONSTITUTION:Input data consisting of m-number of bits is inputted continuously by a clock CLKL of a frequency f0. A voltage controlling oscillator (VCO) 2 receives the clock CLKL and converts the frequency f0 to (m+2)f0/m to generate a new clock CLKH. An (m+2) frequency dividing circuit 3 receives the clock CLKH from the VCO2 and divides it by (m+2) to generate a signal of the time interval corresponding to insertion bits in input data. A speed converting circuit (SPDCONV) 1 receives the clock from the VCO2 and the (m+2) frequency division signal to convert the speed of input data having the frequency f0 to the clock frequency (m+2)f0/m. The output of the SPDCONV1 has a two-bit space at every interval of m-number of bits, and insertion bits P1 are inserted to the space.