| 发明名称 |
LAMINATED CHIP DEVICE |
| 摘要 |
Provided is a laminated chip device including a first laminate in which a plurality of conductor patterns formed on a plurality of sheets are connected to each other through a via formed to penetrate at least a sheet, and a second laminate provided over or below the first laminate and having a plurality of internal electrode patterns formed on a plurality of sheets, and the internal electrode patterns have a non-conductive region in at least a portion of an area corresponding to the via. |
| 申请公布号 |
US2016276995(A1) |
申请公布日期 |
2016.09.22 |
| 申请号 |
US201615073622 |
申请日期 |
2016.03.17 |
| 申请人 |
INNOCHIPS TECHNOLOGY CO., LTD. |
发明人 |
PARK In Kil;NOH Tae Hyung;KIM Gyeong Tae;LEE Myung Ho;SEO Tae Geun;LEE Min Soo;LEE Song Yeon |
| 分类号 |
H03H1/00;H01F27/28;H01G4/30;H01G4/40;H03H7/01;H01G4/005 |
主分类号 |
H03H1/00 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A laminated chip device comprising:
a first laminate including a plurality of conductor patterns respectively provided on a plurality of sheets, the conductor patterns being vertically connected to each other through a via formed to penetrate at least a sheet; and a second laminate disposed over or below the first laminate and including a plurality of internal electrode patterns provided on a plurality of the sheets, wherein the internal electrode patterns are provided with a non-conductive region in at least a portion of an area corresponding to the via. |
| 地址 |
Ansan-Si KR |
