发明名称 PROCESSING SYSTEM OF ASSIGNMENT OF DATA REGISTER
摘要 PURPOSE:To reduce load/store processing in an undesired form, by detecting the existence of a reference arrangement element successively and holding contents of a register, by which the arrangement element is defined, up to the next cycle when a used register is determined. CONSTITUTION:A compiler 18 takes in a source program 17 from a mass storage device and interprets sentences in a source interpreting part 20 to develop them to an intermediate code. A storage allocating part 21 allocates addresses in a storage area to various data appearing in the program, and a vector converting part 22 detects loop structures in the program to recognize parallel executable parts and changes the intermediate code. An intermediate code optimizing part 23 performs the optimization for using effectively a processor in the level of the intermediate code, and a register use determining part 24 assigns resources to data appearing in the intermediate code, and an objective program 19 is outputted from an objective program output part 25. When used registers are determined in the determining part 24, the existence of reference arrangement elements is detected successively, and contents of registers by which arrangement elements are defined are held up to the next cycle, and values of arrangement elements are propagated in the next cycle.
申请公布号 JPS58149543(A) 申请公布日期 1983.09.05
申请号 JP19820031192 申请日期 1982.02.27
申请人 FUJITSU KK 发明人 HIROTA TOSHIAKI;TANAKURA YOSHIYUKI;HIRABAYASHI TOSHIHIRO;TAKIUCHI MASAAKI;AOKI MASAKI
分类号 G06F9/38;G06F9/32;G06F9/44;G06F9/45;G06F17/16 主分类号 G06F9/38
代理机构 代理人
主权项
地址