发明名称 MEMORY ACCESS SYSTEM
摘要 PURPOSE:To operate a storage device without losing an economical property, by sending back a data, etc. accumulated in a data register to a central processing unit, when an address transferred from the central processing unit coincides with accumulated contents of an address register. CONSTITUTION:A storage part MU stores a data, etc. An address register AR accumulates an address a1 transferred from a central processing unit CPU, and a data register DR accumulates a data, etc. extracted from the storage part MU. The address a1 transferred from the central processing unit CPU is collated with accumulated contents a2 of the address register AR by a collating circuit MA, and when the coincidence is detected by this collating circuit MA, the data, etc. accumulated in the data register DR are sent back to the central processing unit CPU. A storage control part MC controls an operation of each part.
申请公布号 JPS5938862(A) 申请公布日期 1984.03.02
申请号 JP19820148907 申请日期 1982.08.27
申请人 FUJITSU KK 发明人 URUSHIBARA TETSUO
分类号 G06F9/38;G06F12/00;G06F12/02;G06F12/04;G06F13/00 主分类号 G06F9/38
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