METHOD OF ESTABLISHING AN OSCILLATOR CLOCK SIGNAL

摘要

A hybrid numeric-analog clock synchronizer, for establishing a clock or carrier locked to a timing reference. The clock may include a framing component. The reference may have a low update rate. The synchronizer achieves high jitter rejection, low phase noise and wide frequency range. It can be integrated on chip. It may comprise a numeric time-locked loop (TLL) with an analog phase-locked loop (PLL). Moreover a high-performance number-controlled oscillator (NCO), for creating an event clock from a master clock according to a period control signal. It processes edge times rather than period values, allowing direct control of the spectrum and peak amplitude of the justification jitter. Moreover a combined clock-and-frame asynchrony detector, for measuring the phase or time offset between composite signals. It responds e.g. to event clocks and frame syncs, enabling frame locking with loop bandwidths greater than the frame rate.

主权项

1. Method of establishing an output clock signal on a basis of an input timing reference, said method comprising the steps of:
attenuating jitter of said input timing reference to produce a control signal; providing at least one intermediate clock signal on a basis of said control signal by justifying at least one of said intermediate clock signals to a local clock and performing spectrum control; providing said output clock signal on a basis of said at least one intermediate clock signal by attenuating jitter of said at least one intermediate clock signal; and providing said output clock signal as an output event clock component and an output framing component; wherein said establishing the output clock signal on the basis of the input timing reference is further based on a stable reference clock, and wherein the method comprises attenuating jitter of said stable reference clock below and above a middle frequency band.