| 摘要 |
A method for controlling memory components of 16K x 1 bit or 64K x 1 bit by employing a control bus adapted to components of 4K x 1 bit, wherein a memory refresh signal (REF) is generated independent of the one supplied by the system. A memory circuit board, particularly, but not exclusively, a memory circuit board for a system for inspecting or testing electronic components, having a capacity of 32K or 64K words of 24 data bits and one parity bit, and including a refresh signal generating block (REFRESH TIMING) operating according to the method defined above. |
