发明名称 LOOP BUS CONTROL SYSTEM
摘要 PURPOSE:To prevent the decrease in transmission efficiency by eliminating a defective frame being left unreceived by a data processor on a loop bus. CONSTITUTION:Suppose that a fault occurs in a data processor B7 connected to the loop bus 1 and a frame transmitted from other data processors to the data processor B7 is left unreceived on the loop bus 1. In this case, a data processor A2 changes the own address value into an address value of the data processor B7 temporarily. Thus, the defective frame left on the loop bus 1 is eliminated and the interference of the defective frame on normal frames is prevented.
申请公布号 JPS59148451(A) 申请公布日期 1984.08.25
申请号 JP19830022558 申请日期 1983.02.14
申请人 NIPPON DENKI KK;NIHON DENKI ENGINEERING KK 发明人 AOYAMA HIDEO;SUGANO HIROYUKI
分类号 G06F13/00;H04L12/437 主分类号 G06F13/00
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